1. Field of the Invention
The present invention relates generally to semiconductor device assemblies, or so-called “multi-chip modules,” and, more specifically, to multi-chip modules in which two or more semiconductor devices are stacked relative to one another. In particular, the present invention relates to stacked semiconductor device assemblies in which the upper semiconductor device of an adjacent pair of semiconductor devices at least partially overlies discrete conductive elements protruding above the lower semiconductor device of the adjacent pair and the distances between adjacent, stacked semiconductor devices are determined, at least in part, by a quantity of adhesive material interposed therebetween.
2. Background of Related Art
In order to conserve the amount of surface area, or “real estate,” consumed on a carrier substrate, such as a circuit board, by semiconductor devices connected thereto, various types of increased density packages have been developed. Among these various types of packages is the so-called “multi-chip module” (MCM). Some types of multi-chip modules include assemblies of semiconductor devices that are stacked one on top of another. The amount of surface area on a carrier substrate that may be saved by stacking semiconductor devices is readily apparent-a stack of semiconductor devices consumes roughly the same amount of real estate on a carrier substrate as a single, horizontally oriented semiconductor device or semiconductor device package.
Due to the disparity in processes that are used to form different types of semiconductor devices (e.g., the number and order of various process steps), the incorporation of different types of functionality into a single semiconductor device has proven very difficult to actually reduce to practice. Even in cases where semiconductor devices that carry out multiple functions can be fabricated, multi-chip modules that include semiconductor devices with differing functions (e.g., memory, processing capabilities, etc.) are often much more desirable since the separate semiconductor devices may be fabricated independently and later assembled with one another much more quickly and cost-effectively (e.g., lower production costs due to higher volumes and lower failure rates).
Multi-chip modules may also contain a number of semiconductor devices that perform the same function, effectively combining the functionality of all of the semiconductor devices thereof into a single package.
An example of a conventional, stacked multi-chip module includes a carrier substrate, a first, larger semiconductor device secured to the carrier substrate, and a second, smaller semiconductor device positioned over and secured to the first semiconductor device. The second semiconductor device does not overlie bond pads of the first semiconductor device and, thus, the second semiconductor device does not cover bond wires that electrically connect bond pads of the first semiconductor device to corresponding contacts or terminals of the carrier substrate. As the bond pads of each lower semiconductor device are not covered by the next higher semiconductor device, vertical spacing between the semiconductor devices is not important. Thus, any suitable adhesive may be used to secure the semiconductor devices to one another. Such a multi-chip module is disclosed and illustrated in U.S. Pat. No. 6,212,767, issued to Tandy on Apr. 10, 2001 (hereinafter “the '767 patent”). As the sizes of the semiconductor devices of such a multi-chip module must continue to decrease as they are positioned increasingly higher on the stack, the obtainable heights of such multi-chip modules become severely limited.
Another example of a conventional multi-chip module is described in U.S. Pat. No. 5,323,060, issued to Fogal et al. on Jun. 21, 1994 (hereinafter “the '060 Patent”). The multi-chip module of the '060 Patent includes a carrier substrate with semiconductor devices disposed thereon in a stacked arrangement. The individual semiconductor devices of each multi-chip module may be the same size or different sizes, with upper semiconductor devices being either smaller or larger than underlying semiconductor devices. Adjacent semiconductor devices of each of the multi-chip modules disclosed in the '060 Patent are secured to one another with an adhesive layer. The thickness of each adhesive layer well exceeds the loop heights of wire bonds protruding from a semiconductor device upon which that adhesive layer is to be positioned. Accordingly, the presence of each adhesive layer prevents the back side of an overlying, upper semiconductor device from contacting bond wires that protrude from an immediately underlying, lower semiconductor device of the multi-chip module. The adhesive layers of the multi-chip modules disclosed in the '060 Patent do not encapsulate or otherwise cover any portion of the bond wires that protrude from any of the lower semiconductor devices. It does not appear that the inventors named on the '060 Patent were concerned with overall stack heights. Thus, the multi-chip modules of the '060 Patent may be undesirably thick due to the use of thick spacers or adhesive structures between each adjacent pair of semiconductor devices, resulting in wasted adhesive and excessive stack height.
A similar but more compact multi-chip module is disclosed in U.S. Pat. Re. 36,613, issued to Ball on Mar. 14, 2000 (hereinafter “the '613 Patent”). The multi-chip module of the '613 Patent includes many of the same features as those disclosed in the '060 Patent, including adhesive layers of carefully controlled thicknesses that space vertically adjacent semiconductor devices apart a greater distance than the loop heights of wire bonds protruding from the lower of the adjacent dice. The use of thinner bond wires with low-loop profile wire bonding techniques permits adjacent semiconductor devices of the multi-chip module disclosed in the '060 Patent to be positioned more closely to one another than adjacent semiconductor devices of the multi-chip modules disclosed in the '060 Patent. Nonetheless, an undesirably large amount of additional space may remain between the tops of the bond wires protruding from one semiconductor device and the back side of the next higher semiconductor device of such a stacked multi-chip module.
Conventionally, when a particular amount of spacing is needed between semiconductor devices to separate discrete conductive elements, such as bond wires, that protrude above an active surface of one semiconductor device from the back side of the next higher semiconductor device, the semiconductor devices of stacked multi-chip modules have been separated from one another with spacers. Exemplary spacers that have been used in stacked semiconductor device arrangements have been formed from dielectric-coated silicon or a polyimide film. An adhesive material typically secures such a spacer between adjacent semiconductor devices. The use of such preformed spacers is somewhat undesirable since an additional alignment and assembly step is required for each such spacer. Proper alignment of a preformed spacer with a semiconductor device requires that the spacer not be positioned over bond pads of the semiconductor device. In addition, if a preformed spacer is placed on the surface of a semiconductor device that has already been electrically connected to a substrate, the spacer must be positioned in such a manner that the often delicate discrete conductive elements, such as bond wires, extending from the bond pads of the semiconductor device not be damaged. As those of skill in the art are aware, improper alignment and placement of such a preformed spacer may increase the likelihood that a semiconductor device may be damaged, thereby decreasing overall product yields.
The vertical distance that adjacent semiconductor devices of a stacked type multi-chip module are spaced apart from one another may be reduced by arranging the immediately underlying semiconductor devices such that upper semiconductor devices are not positioned over bond pads of immediately lower semiconductor devices or bond wires protruding therefrom. Thus, adjacent semiconductor devices may be spaced apart from one another a distance that is about the same as or less than the loop heights of the wire bonds that protrude above the active surface of the lower semiconductor device. U.S. Pat. No. 6,051,886, issued to Fogal et al. on Apr. 18, 2000 (hereinafter “the '886 Patent”), discloses such a multi-chip module. According to the '886 Patent, wire bonding is not conducted until all of the semiconductor devices of such a multi-chip module have been assembled with one another and with the underlying carrier substrate. The semiconductor devices of the multi-chip modules disclosed in the '886 Patent must have bond pads that are arranged on opposite peripheral edges. Semiconductor devices with bond pads positioned adjacent the entire peripheries thereof could not be used in the multi-chip modules of the '886 Patent. This is a particularly undesirable limitation due to the ever-increasing feature density of state-of-the-art semiconductor devices, which is often accompanied by a subsequent need for an ever-increasing number of bond pads on semiconductor devices.
In view of the foregoing, it appears that a method for forming stacked semiconductor device assemblies which reduces the likelihood of damage to semiconductor devices and associated wire bonds, as well as provides flexibility in bond pad number and placement, would be useful.